Magnetic Random Access Memory (MRAM) is non-volatile memory in which data is stored by programming a Magnetic Tunnel Junction (MTJ). MRAM is advantageous because the MTJ can be used to store information even when power is turned off. Data is stored in the MTJ as a small magnetic element (e.g., a magnetic state) rather than an electric charge or current, and the stored data can then be sensed by measuring resistance associated with the MTJ without disturbing the magnetic state. An exemplary MTJ 10 is illustrated in FIG. 1. Data is stored in the MTJ 10 according to the magnetic orientation between a free layer 12 and a pinned layer 14, which are magnetically polarized plates formed from a ferromagnetic material. The pinned layer 14 is a permanent magnet set to a particular polarity, while a polarity of the free layer 12 will change to match that of a sufficiently strong external field. The MTJ 10 is configured in a conventional “bottom-spin valve” configuration wherein the pinned layer 14 is disposed below the free layer 12. The free layer 12 and the pinned layer 14 are separated by a tunnel junction or barrier 16 formed from a thin non-magnetic dielectric layer. The free layer 12 and the pinned layer 14 can store information even when the magnetic H-field is ‘0’ due to a hysteresis loop 18 of the MTJ 10. Electrons can tunnel through the tunnel barrier 16 if a bias voltage is applied between two electrodes 20 and 22 coupled on ends of the MTJ 10. The tunneling current depends on the relative orientation of the free layer 12 and the pinned layer 14. When using a Spin-Transfer Torque (STT) MTJ, the difference in the tunneling current as the spin alignment of the free layer 12 and the pinned layer 14 is switched between parallel (P) and anti-parallel (AP) states is known as the Tunnel Magnetoresistance Ratio (TMR).
When the magnetic orientation of the free layer 12 and the pinned layer 14 are of opposite polarization (shown in FIG. 1 as MTJ 10′), the anti-parallel (AP) state exists (e.g., a logical ‘1’). On the other hand, when the magnetic orientation of the free layer 12 and the pinned layer 14 are of the same polarization (shown in FIG. 1 as MTJ 10″), the parallel (P) state exists (e.g., a logical ‘0’). The magnetic orientation of the free layer 12 and the pinned layer 14 can be sensed to read data stored in the MTJ 10 by measuring the resistance that results when current flows through the MTJ 10, wherein the resistance will be low when the P state exists and the resistance will be higher when the AP state exists. Data can also be written and stored in the MTJ 10 by applying a magnetic field to change the magnetic orientation of the free layer 12 to either a P or AP magnetic orientation with respect to the pinned layer 14. In other words, as noted above, the magnetic orientation of the free layer 12 can be changed, but the magnetic orientation of the pinned layer 14 is fixed.
FIG. 2 illustrates an STT MTJ 23 (referred to herein as “MTJ 23”) having a similar design to the MTJ 10 shown in FIG. 1 and described above. The MTJ 23 is provided as part of an MRAM bitcell 24 to store non-volatile data. The MRAM bitcell 24 may be provided in a memory array and used as memory storage for any type of system requiring electronic memory, such as a computer processing unit (CPU) or processor-based system, for example. A metal-oxide semiconductor (typically n-type MOS, i.e., NMOS) access transistor 26 is provided to control reading and writing to the MTJ 23. The access transistor 26 has a drain (D) coupled to a bottom electrode 22 of the MTJ 23, which is coupled to the pinned layer 14. A word line (VWL) is coupled to a gate (G) of the access transistor 26, while a source (S) of the access transistor 26 is coupled to a voltage source (VS). A bit line (VBL) is coupled to a top electrode 20 of the MTJ 23, which is coupled to the free layer 12.
When reading data stored in the MTJ 23, the bit line (VBL) is activated for the access transistor 26 to allow current to flow through the MTJ 23 between the top electrode 20 and the bottom electrode 22. As noted above, a low resistance, as measured by voltage applied on the bit line (VBL) divided by the current flowing through the MTJ 23, is associated with a P orientation between the free layer 12 and the pinned layer 14, whereas a higher resistance is associated with an AP orientation between the free layer 12 and the pinned layer 14. As such, due to the tunneling magnetoresistance effect, the electrical resistance of the MRAM bitcell 24 varies depending on the relative orientation between the polarities of the free layer 12 and the pinned layer 14, whereby measuring the current that flows through the MTJ 23 when the bit line (VBL) is activated may indicate the electrical resistance of the MRAM bitcell 24 and the relative orientation between the polarities of the free layer 12 and the pinned layer 14.
When writing data to the MTJ 23, the word line (VWL) is activated to activate the gate (G) of the access transistor 26. A voltage differential between the bit line (VBL) and the source line (VS) is applied. As a result, a write current (I) is generated between the drain (D) and the source (S). To change the MTJ 23 from the AP state to the P state, a write current (IAP-P) flowing from the top electrode 20 to the bottom electrode 22 is generated, which induces an STT at the free layer 12 to change the magnetic orientation of the free layer 12 to P with respect to the pinned layer 14. To change the magnetic orientation of the MTJ 23 from the P state to the AP state, a write current (IP-AP) flowing from the bottom electrode 22 to the top electrode 20 is generated, in which case the STT induced at the free layer 12 changes the magnetic orientation of the free layer 12 to AP with respect to the pinned layer 14.
MRAM has the potential to be a promising memories solution for embedded systems, mobile systems, and other memory markets due to having less demanding requirements than standalone memory, including high density, high speed performance, high endurance, and small cell size, among other things. However, MRAM bitcells that only have one MTJ (e.g., as shown in FIGS. 1 and 2) typically have a storage capacity that is not large enough to complete with existing memory solutions such as static or dynamic RAM. As such, Multi-Level Memory Cells (MLCs) that include multiple MTJ structures have been proposed to provide greater memory density in circuits, applications, or other systems that employ MRAM. For example, FIG. 3 illustrates an exemplary prior art Multi-Level Memory Cell (MLC) 34 using multiple MTJ structures, which are represented in FIG. 3 as series-stacked MTJ1 33a and MTJ2 33b. By having MTJ1 33a and MTJ2 33b stacked in series, as shown in circuit diagram 36, the MLC 34 can be configured to have four different resistance states by combining the possible magnetic orientations associated with each of MTJ1 33a and MTJ2 33b. In particular, MTJ1 33a and MTJ2 33b can each have a parallel (P) or anti-parallel (AP) state, such that the MLC 34 can combine the possible P or AP states associated with each of MTJ1 33a and MTJ2 33b to achieve four possible states.
For example, as shown in circuit diagram 38, the four possible states may include a logical ‘00’ (i.e., when MTJ1 33a and MTJ2 33b both have the P state), a logical ‘10’ (i.e., when MTJ1 33a has the AP state and MTJ2 33b has the P state), a logical ‘01’ (i.e., when MTJ1 33a has the P state and MTJ2 33b has the AP state), and a logical ‘11’ (i.e., when MTJ1 33a and MTJ2 33b both have the AP state). However, in order to achieve the four possible states, the series stacked MTJ1 33a and MTJ2 33b must have different threshold currents and resistance variations in order to allow separate switching between MTJ1 33a and MTJ2 33b. To achieve this objective, the prior art MLC 34 shown in FIG. 3 includes a design whereby MTJ1 33a has an area half that of MTJ2 33b, and consequently, the resistance in MTJ1 33a will be half that of MTJ2 33b and the current flowing through MTJ1 33a will be double that flowing through MTJ2 33b. However, this design suffers from various drawbacks and disadvantages, including that one of the most significant factors determining the cost of a memory system is the manufacturing process, with more mask processes contributing to increased overall manufacturing costs. As such, the MLC 34 shown in FIG. 3 may substantially increase manufacturing costs because different masks would be required to fabricate MTJ1 33a and MTJ2 33b due to their different areas. Accordingly, because processing cost is a serious consideration in implementing features in an integrated circuit device, a need exists for an improvement in MRAM design and process flows, as eliminating the need for even one mask and associated processes can save significant fabrication costs.